1. Field of the Invention
The present invention relates to an improvement of a multiprocessor system which utilizes a page mode memory as a common memory for a master processor and a plurality of slave processors. More particularly, the invention relates to an improvement of such a multiprocessor system for reducing the adverse effects upon the performance of the master processor of memory accesses which are executed by the slave proccessors
2. Prior Art Technology
In recent years, a type of memory known as a page mode memory has come into widespread application as a common memory of a multiprocessor system, i.e. which is accessed in common by the master processor and the slave processors of that system, which are linked via a common address bus and a common data bus (or a single bus which provides both address and data transfer functions by multiplexed operation) to the page mode memory. A page mode memory is generally of DRAM (dynamic random access memory) type. Each memory address consists of a portion referred to in the following as a page address (where a page consists of a fixed number of successively adjacent addresses within a specific region of the memory), and a portion which represents the position of the address within that page (the latter portion being referred to in the following as an intra-page address). Accessing of an address of the page mode memory by a processor may be executed in two consecutive periods (such an access being referred to in the following as a long access), with the processor (master processor or slave processor) first outputting to the page mode memory the required page address and a page load command. When these are received by the page mode memory, the data of that page are loaded into a page buffer, which is an integral part of the page mode memory and from which respective addresses within the page can be rapidly accessed using the intra-page addresses. However the configuration of a page mode memory to which the present invention is applicable is not limited to such an arrangement. Next, the processor outputs to the page mode memory the intra-page address and accesses that address, e.g. by writing or reading data to or from the address.
Once such a long access has been executed, then thereafter, so long as the processor continues to access only addresses which lie within the page that has been loaded into the page buffer of the page mode memory, it is only necessary for the processor to output to the page mode memory the intra-page address of a desired address in order to access that address. Such a type of access will be referred to in the following as a short access.
The above is illustrated in the example of FIG. 10. The upper part of FIG. 10 shows two program sequences which are to be respectively executed in parallel by the master processor and one of the slave processors of a prior art multiprocessor system which utilizes a page mode memory. In each program, "access" denotes a page mode memory access instruction, and for example "access p/a" signifies "access the (intra-page) address a within the page p (more specifically, the page having the page address p)". In each program "others" signifies any instruction other than a memory access instruction. The lower part of FIG. 10 shows the respective sequences of operations that are actually executed in parallel by the master processor and slave processor, to execute the respective program instruction sequences. In the step "access p", the master processor outputs to the page mode memory the page address p and a command for loading that page into the page buffer of the memory. Next, in the second operating step of the long access, the master processor outputs to the memory the intra-page address a, and that address is then accessed by the master processor. While the master processor is doing this, the slave processor must wait for one operating period (as indicated by "nop"), then the slave processor begins a long access in which the page g is first loaded into the page buffer, then the intra-page address e within that page is accessed by the slave processor.
However, since the page mode memory is being used in common by the master processor and slave processor, when the master processor subsequently has to again access an address within the page p, i.e. after executing the instruction "other 5", it is necessary for the master processor to again execute a long access, i.e. to again send the page address p to the memory to load that page into the page buffer, then to access the required address b within that page. It can be understood that if there had been no memory access by a slave processor to a page which is different from page p during the interval between the accessing of address a and address b by the master processor, it would not have been necessary to re-load the page p into the page buffer of the memory, i.e. it would only have been necessary to execute a short access. Thus, in a prior art multiprocessor system which utilizes a page mode memory as a common memory of the system, each time that the master processor of the system is executing successive accesses to addresses within a single page, and a slave processor executes a memory access (intervening between these successive accesses by the master processor) to a page which is different from that being accessed by the master processor, the speed of program execution by the master processor is correspondingly slowed. Since the performance of the system is essentially determined by that of the the master processor, the system performance is lowered as a result.
This is a significant problem since, in practice, it is necessary for the slave processors to access addresses within a different region or regions of the memory from the memory region or regions accessed by the master processor. Thus, it is almost certain that when a slave processor accesses the memory, it will access a different page from the last page that was accessed by the master processor.
As a result, such a prior art type of multiprocessor system utilizing a common page mode memory cannot benefit fully from the basic advantage of using a page mode memory, i.e. a reduction of the average memory access time.